LT DIN Rail Analog Transmitters with Serial Data Communication and Analog outputs for DC Voltage and Current Input Signal Applications

DC Voltage & Current DIN Rail Transmitter Frequently Asked Questions

Why is display update rate (3.5/s at 60 Hz) so much slower than the A-to-D conversion rate (60/s at 60 Hz)?

Documented specification specifically separates these as distinct stages — the A-to-D conversion rate reflects how fast the internal converter produces raw readings, while the display update rate reflects how often the human-readable display refreshes; the display is documented as intentionally updated less frequently than the underlying conversion rate, since a display refreshing 60 times per second would be unreadable, while the faster internal conversion rate still supports peak/valley capture and fast analog/serial output updates.

Why do the 200.00 mV and 2.0000V ranges specifically get 1 GΩ input impedance while other voltage ranges don't?

These two lowest voltage ranges are documented as having 1 GΩ impedance specifically to minimize loading on the voltage signal — low-level millivolt and low-volt sources are typically higher-impedance and more easily loaded down by a measuring instrument's own input resistance, so the documented extra-high impedance on these specific low-level ranges protects measurement accuracy where loading effects would otherwise be most significant.

Why does the 5A current range use a built-in shunt rather than a direct current-sensing input like the lower current ranges?

Documented design specifically describes the 5A range as measuring the IR drop across a built-in 10 milliohm current shunt — at 5 amps, this produces a small but measurable voltage the transmitter's voltage-sensing circuitry can read, which is a standard, documented approach for extending accurate current measurement to higher current levels without needing separate high-current-rated signal conditioning electronics.

Does the ±0.4V accuracy figure on the 600V range mean this range is inherently less accurate than the other voltage ranges?

In absolute terms, yes, and this is documented explicitly rather than hidden — while other voltage ranges are specified as 0.01% FS ±2 counts, the 600V range's documented accuracy is a flat ±0.4V, reflecting the practical accuracy tradeoff of extending measurement to a very high voltage range; this figure is a genuine, stated exception rather than following the same percentage-based formula as the other ranges.

Can the Extended computer board's custom curve linearization be applied to the current input ranges, or only voltage ranges?

Documented example specifically illustrates custom curve linearization using a 4-20 mA level transmitter for tank volume calculation — since this documented example is itself a current-input application, custom curve linearization is not described as limited to voltage ranges only; the same 180-point spline-fit approach applies to whichever range and signal type the transmitter is configured for.

Does choosing RS485 instead of RS232 change the transmitter's measurement accuracy or A-to-D conversion rate?

No — the documented RS232/RS485 selection is specifically a jumper-selectable choice governing the serial communication signal type and multi-drop capability, entirely separate from the documented A-to-D conversion technique, rate, and accuracy specifications; switching communication interfaces doesn't affect how the transmitter measures or converts its input signal.

If up to 30 LT Transmitters are daisy-chained on RS485, does each one need a fully independent power supply, or can power also be shared or chained?

Documented specification addresses power and communications as separate systems — the RS485 daisy-chain specifically describes the data connection method, while each transmitter's power input (85-264 Vac/90-300 Vdc standard, or 10-48 Vdc/12-32 Vac optional low-power) is specified independently per unit; the page doesn't describe a shared or chained power arrangement, so each transmitter is treated as needing its own power connection.

Does the overcurrent protection multiplier (such as 25x for the 2 mA range) mean the transmitter can be safely operated continuously at that overcurrent level?

No — documented overcurrent protection multipliers describe the transmitter's tolerance for a fault or transient overcurrent condition without damage, not a rating for safe continuous operation at that elevated level; normal operation is expected to stay within the range's specified full-scale rating, with the overcurrent multiplier serving as a protective margin against unexpected signal excursions or wiring faults.

Does the analog output's 0.02% accuracy figure combine with the input conversion accuracy, or replace it?

Documented specification specifically describes analog output accuracy as "0.02% of output span plus conversion accuracy" — meaning these two error sources are additive rather than one superseding the other; the total end-to-end accuracy of a retransmitted 4-20 mA or 0-10V output reflects both the original input measurement's own accuracy and the additional error the output conversion stage itself contributes.

Does the transducer excitation output share the same isolation as the analog signal output, or is it a separate isolation boundary?

Documented specification lists these as separately rated isolation boundaries — the excitation output is specified as 50 Vdc isolation from signal ground, while the analog output and serial data output each carry their own documented 250V rms working / 2.3 kV rms test isolation rating; these are independently specified isolation barriers rather than one shared rating covering every output on the transmitter.

Integrating ADC & Power-Line Noise Rejection Questions From the Field

Why does integrating the input signal over exactly one power-line cycle specifically reject 50/60 Hz noise?

Documented technical explanation specifically describes this as a mathematical consequence of the integration process: input frequencies with periods equal to, or an exact sub-multiple of, the chosen integration time average out to zero over that fixed interval — choosing an integration time matched to one complete power-line cycle means the line-frequency noise component contributes essentially nothing to the final integrated result.

Does an integrating ADC reject only the fundamental 50/60 Hz frequency, or does it also help with harmonics of that frequency?

It rejects harmonics too, by the same documented mechanism — since rejection applies to any frequency whose period is an integer sub-multiple of the integration time, not just the fundamental, documented analysis specifically notes that for a 100 ms integration time, all multiples of 10 Hz are theoretically rejected, which inherently includes the harmonics of 50 Hz and 60 Hz line frequency along with the fundamentals themselves.

Is power-line noise rejection from an integrating ADC theoretically perfect, or are there documented practical limitations?

Documented technical analysis specifically identifies real limitations: rejection is described as complete only in theory, with actual performance limited by the finite signal swing of the integrator (since it can't be allowed to saturate) and by the inevitable small "wobble" or drift of the actual power-line frequency away from its nominal 50 Hz or 60 Hz value in real electrical systems.

Does a 2-3 Hz drift in actual power-line frequency (which is documented as normal) meaningfully degrade an integrating ADC's noise rejection?

It can, according to documented analysis — since the integrating architecture's excellent rejection specifically depends on the integration time being precisely matched to the actual line-frequency period, real-world line frequency deviations of up to roughly 2-3 Hz are documented as a genuine, normal occurrence that this simple fixed-time architecture doesn't automatically compensate for, motivating more advanced architectures specifically designed to remain robust against such line-frequency variation.

Why do integrating ADCs remain a common architecture choice for precision digital voltmeters and similar instrumentation despite being relatively slow?

Documented tradeoff analysis specifically identifies the combination of excellent noise rejection, high linearity (since conversion is time-based rather than amplitude-based), simple analog front-end circuitry, and strong stability against component and temperature variation as the reasons this architecture remains well-suited to high-resolution, precision-focused applications, even though the same fixed integration time that provides its noise rejection inherently limits its maximum conversion speed.

Is common-mode rejection (CMR) the same thing as normal-mode rejection (NMR), or do they address different noise paths?

Documented distinction specifically separates these: common-mode noise (most commonly power-line-coupled noise appearing identically on both signal input lines relative to ground) is addressed by a front-end's CMRR, while normal-mode rejection specifically addresses noise that appears as an actual voltage difference across the signal input itself — CMRR and NMRR are documented as complementary, addressing genuinely different noise coupling paths rather than being interchangeable terms for the same phenomenon.

Do sigma-delta ADCs achieve power-line noise rejection through the same integration mechanism as classic dual-slope integrating ADCs?

Not identically, though the underlying goal is documented as the same — sigma-delta converters are documented as commonly using a digital filter (such as a sinc3 filter) with its response tuned to place notches at the target line frequencies, achieving strong rejection (over 100 dB in some cited configurations) through digital filtering after conversion, rather than through the analog integration-over-a-fixed-time-window mechanism that defines classic dual-slope or Concurrent Slope architectures.

Can amplifier gain by itself meaningfully improve rejection of power-line noise before it even reaches the ADC?

Indirectly, yes — documented analysis of a precision signal-conditioning front-end specifically notes that increasing front-end gain increases sensitivity relative to a fixed level of extrinsic common-mode noise (such as power-line coupling), and that documented common-mode rejection ratio (CMRR) itself increases with gain in typical differential front-end designs — meaning gain stage design contributes to overall noise rejection performance alongside, not instead of, the ADC's own rejection mechanism.